An image capturing device including a CMOS (Complementary Metal Oxide Semiconductor) image sensor is applied to a digital camera or the like, for example. Such an image capturing device has a pixel region and a peripheral circuit region, the pixel region being provided with a photo diode for converting incoming light into a charge, the peripheral circuit region being provided with a peripheral circuit for processing, as an electric signal, the charge converted by the photo diode. In the pixel region, the charge generated in the photo diode is transferred to a floating diffusion region by a transfer transistor. The transferred charge is converted into an electrical signal by an amplification transistor in the peripheral circuit region, and is output as an image signal. As documents disclosing such an image capturing device, there are Japanese Patent Laying-Open No. 2010-56515 (Patent Document 1) and Japanese Patent Laying-Open No. 2006-319158 (Patent Document 2).
For high sensitivity and low power consumption, size reduction of image capturing devices is being attempted. When the gate length of a gate electrode of a field effect transistor processing an electrical signal becomes not more than 100 nm as a result of the size reduction, an approach has been taken to improve transistor characteristics while securing an effective gate length. Specifically, before forming a sidewall insulating film, extension implantation (LDD (Lightly Doped Drain) implantation) is performed with an offset spacer film being formed on the side wall surface of the gate electrode. Accordingly, the effective gate length of the field effect transistor is secured.